The present invention relates to an apparatus for verifying the data retention in non-volatile memories, particularly in EPROM memories. More particularly such invention relates to an apparatus for verifying the data retention in EPROM memories in an integrated circuit.
In the manufacturing of integrated circuits it is possible to incur in the manufacturing of non-volatile memory cells which can show defects in data storage and which can carry to the failure of a device wherein they are comprised. Also the memory cells must be tested in order to detect the defective cells which will be eliminated.
In the case wherein a non-volatile memory is used in an integrated circuit, it is necessary to have a circuitry in order to effectuate the data retention tests in each single memory cell. Such operations must consider the possibility to effectuate thermal stress simulations to which a device containing the non-volatile memory will be subjected after the assemblage on the final chip.
The circuitry which must be performed to satisfy such needs must be as little bulky as possible and it must increase as little as possible the time to effectuate such test.
A latch matrix, per se, used for block 12 is of a type well known in the art and thus the details need not be described.
According to the present invention, an apparatus for verifying the data retention in a non-volatile memory comprising at least one multiplexer and at least one shift register, is provided. The multiplexer and shift register are disposed so that the data of the non-volatile memory are input to the multiplexer. The output of the multiplexer is in turn input to the shift register. A logical circuit using suitable commands controls the transfer of data from the multiplexer to the shift register, the loading of data and the shifting of output data from the shift register.
Thanks to the present invention, it is possible to provide an apparatus for verifying the data retention in non-volatile memories which is small in size, which is fast and which provides the assurance of the reliability of the memory cells.